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3.514187e+000 2.488700e+001 facet normal -0.88076 0.468307 -0.0703597 vertex 8.549 4.11698 6.17306 facet normal 8.724512e-001 3.884454e-003 4.886858e-001 vertex -4.034391e+000 -5.128616e-002 2.480400e+001 facet normal -0.815358 0.435818 0.381123 facet normal -0.634395 0.773009 0 facet normal -0.63014 0.772994 0.0735165 facet normal -4.496502e-001 -7.868875e-001 4.226378e-001 vertex 7.506481e-001 5.373734e+000 2.480400e+001 facet normal -8.396846e-02 9.964684e-01 0.000000e+00 facet normal 8.314790e-01 -5.555561e-01 3.284580e-04 facet normal 0.184972 0.225389 0.956549 facet normal -0.0156291 -0.0930619 0.995538 vertex 3.4084 7.24322 19.9492 facet normal 0.0822199 0.0560555 -0.995037 vertex -10.0942 -0.0912724 0.0491304 vertex -0.589247 9.84902 1.31504 vertex -0.663325 10.0728 0.0491304 vertex 7.12392 -6.81517 1.35836 facet normal -0.586516 -0.714676 0.3811 facet normal -3.036606e-01 -9.527803e-01 0.000000e+00 vertex -1.001369e+02 1.055465e+02 3.455000e+01 facet normal 3.899954e-15 -1.000000e+00 -9.660595e-15 facet normal 9.017105e-001 4.415479e-003 4.323179e-001 facet normal 0.290264 0.956873 -0.0119204 facet normal -8.416038e-01 3.471391e-03 -5.400843e-01 facet normal -0.181193 0.229543 0.956284 facet normal 0.0580967 0.0922853 0.994036 facet normal -3.562750e-001 6.107888e-001 7.071105e-001 facet normal 1.398071e-01 -9.901788e-01 0.000000e+00 vertex -1.042160e+02 9.665134e+01 2.550000e+00 facet normal 0.0895168 -0.0427047 0.995069 vertex -6.83882 4.66263 19.9688 facet normal 0.680175 0.733049 -0 facet normal -0.290412 -0.956902 -3.99024e-06 facet normal 0.877731 0.469113 0.0975757 vertex 7.48323 5.00013 3 vertex -8.99167 0 3 0 ENDBLK 5 21 330 1F 100 AcDbEntity 67 1 8 0 100 AcDbBlockBegin 2 *PAPER_SPACE 1 (min_thickness 0.254) (filled_areas_thickness no min_thickness 0.25) (filled_areas_thickness no Binary files /dev/null and b/sr1_full.png differ aac0a4a5b4 Notes from debugging Clock POT is too small for a single 0.25 mm² wires, basic insulation, conductor diameter 0.5mm, outer diameter 2.3mm, size source Multi-Contact FLEXI-E_0.25 (https://ec.staubli.com/AcroFiles/Catalogues/TM_Cab-Main-11014119_(en)_hi.pdf), bend radius 3 times outer diameter, generated with kicad-footprint-generator JST PUD series connector, 53780-0670 (), generated with kicad-footprint-generator connector TE MATE-N-LOK side entry JST XH series connector, SM05B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator Molex MicroClasp Wire-to-Board System, 55935-0810, with PCB locator, 7 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator Molex Panelmate series connector, S10B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py Texas instruments QFN Package, datasheet: https://www.ti.com/lit/ds/symlink/tpsm53602.pdf Texas Instruments, DSBGA, area grid, YBJ0008 pad definition, 0.8875x1.3875mm, 5 Ball, 2x3 Layout, 0.35mm Pitch, https://www.st.com/resource/en/datasheet/stm32h725vg.pdf ST WLCSP-115, ST die ID 469, 4.02x4.27mm, 81 Ball, 9x9 Layout, 0.4mm Pitch, https://www.st.com/resource/en/datasheet/stm32g031y8.pdf ST WLCSP-20, ST die ID 483, 3.73x4.15mm, 115 Ball, X-staggered 7x5 Layout, 0.4mm Pitch, https://assets.nexperia.com/documents/data-sheet/PCMFXUSB3S_SER.pdf ST WLCSP-18, ST Die ID 466, 1.86x2.14mm, 18 Ball, X-staggered 21x11 Layout, 0.4mm Pitch, https://www.st.com/resource/en/datasheet/stm32g491re.pdf ST WLCSP-81, ST die ID 494, 3.3x3.38mm, 49 Ball, 7x7 Layout, 0.8mm Pitch, https://www.nxp.com/docs/en/package-information/98ASA00855D.pdf#page=1 TFBGA-196, 11.0x11.0mm, 196 Ball, 14x14 Layout, 0.75mm Pitch, http://ww1.microchip.com/downloads/en/DeviceDoc/SAMA5D2-Series-Data-Sheet-DS60001476C.pdf#page=2956 FBGA-78, 10.6x7.5mm, 78 Ball, 9x13 Layout, 0.8mm Pitch, https://www.ti.com/lit/ml/mpbg777/mpbg777.pdf BGA 289 0.8 ZAV S-PBGA-N289 Texas Instruments, DSBGA, area grid, YBG pad definition.

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