3
1
Back

Notice and this is the decade counter expects CLOCK to pass 1/2 of V+ (i.e. 6v) but many external clock sources cycle between 0v and 5v max // gate out (j4/j10) // clock out (j5/j12) // glide atten (rv15 // 13 SPDT switches: // 1 for 5v / 2.5v output mode // 10 LEDs 3 sockets Subject: [PATCH] Apply jlcpcb's design rules, small fixes for those .

New Pull Request