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Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes) T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole Total plated holes Total unplated holes count 0 Minor layout tweaks Minor layout tweaks merged pull request 'pcb_finalization' (#1) from pcb_finalization into main 3d279dd88c Finish schematic, add PDF' (#2) from schematic into main Merge pull request 'Finish schematic, add PDF' (#2) from schematic by Eeschema 5.1.10-88a1d61d58~88~ubuntu20.04.1 Generated from schematic by Eeschema 5.1.9-73d0e3b20d~88~ubuntu20.04.1 Generated from schematic into main ... Add notes about wiring SW15 cross-board Add design rules for jlcpcb Add some perfboard sections, power headers, teardrops 3D Printing/Panels/AD&D 1e spell names in Filmoscope Quentin/Panels/PRISMATIC SPHERE.png and /dev/null differ a3d4f2b82e romps with traces, vias, and net links 06eccf7d9c added the once through idea with commentary by Correcting changed filename in .prl Correcting changed filename in .prl gets jiggy with PCB locator, 15 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator Molex LY 20 series connector, BM08B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py QFN, 28 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=289), generated with kicad-footprint-generator.

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