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Back1' a704d3e530 More traces and vias, and net links Panels/FireballSpellVertSmall.png Normal file Unescape Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole) Total plated holes count 16 ============================================================= Total unplated holes count 16 ============================================================= Total unplated holes count 0 Minor layout tweaks Finish schematic, add PDF Schematics/Fireball_VCO.pdf | Bin 0 -> 37432 bytes Panels/futura medium bt.ttf | Bin 11930 -> 0 bytes Latest commits for file Schematics/SynthMages.pretty/C_Rect_L22.0mm_W6.1mm_P20mm_MKT_BIG_RED_CAP.kicad_mod (grid_origin -1.27 106.172 (grid_origin 121.92 119.38 "Notes": "Layer F.SilkS" "Notes": "Layer F.SilkS" "Notes": "Layer F.Mask" "Notes": "Layer B.SilkS" ; DRILL.
- 160 129.5 (end 160.35 131.75 (end.
- SMT Common Mode Choke, https://www.coilcraft.com/pdfs/0805usb.pdf Coilcraft 1812CAN.