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BackSimulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 Not plated through holes are merged with plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) Total plated holes unplated through holes: ============================================================= 2cddc4d62d38c9e1b69839f92a19e7915eecbceb 77735c00cc3285131373f5cfc61b82eab5963d12 Update README.md acf6d57d9f34ce2c424f4c9834d80264fa5ffd89 @circuitlocution.com renamed repository from precadsrprecadsr to synth_mages/MK_VCO Forget (and ignore) fp-info-cache file as it is machine-specific data v1.0 Final revision; added custom DRC as project file tstamp eb945be1-4d1d-46b5-b945-d4ebde74dae2) Final revision; added custom DRC as project file tstamp eb945be1-4d1d-46b5-b945-d4ebde74dae2) Final revision; added custom DRC as project file.
- PI*KnobDiameter; Knurls = round(KnobCircumference/DistanceBetweenKnurls.
- 18mm Transformer, Toroid, tapped, horizontal, laying, Diameter 10,5mm.