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Back\#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= 5ff3077e8252367b7eceb0b21b0803904b695d42 bacdac34d747275148c56e8293dc209c2e326fe4 531ebcae92ad8ad00635060e3583259ee13cc12b Add html test version facet normal 0.865136 -0.462421 0.194181 facet normal -0.129508 0.7808 0.611211 facet normal 0.55474 0.0546157 0.830229 vertex 9.28685 1.84727 3.54602 vertex -6.89148 6.89148 3.26879 facet normal -0.796858 0.241725 0.553703 facet normal 0.109809 0.552145 -0.826485 facet normal -0.111554 0.367742 0.923213.
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