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From 40588ba725f2f6c7240cc5d95c2a8af539e27e15 Mon Sep 17 00:00:00 2001 Subject: [PATCH 09/18] Apply jlcpcb's design rules, small fixes for those Apply jlcpcb's design rules, small fixes for those Fireball/Fireball.kicad_pro | 4 .../PCB/precadsr_Gerbers/precadsr-F_SilkS.gbr | 1166 .../PCB/precadsr_Gerbers/precadsr-NPTH.drl | 4 README.md | 12 delete mode 100644 Hardware/Panel/precadsr_panel_al/precadsr_panel_al.kicad_pcb create mode 100644 Hardware/Panel/precadsr_panel_al_Gerbers/precadsr_panel_al-F_Cu.gbr create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Potentiometer_Alpha_RA6020F_Single_Slide.kicad_mod create mode 100644 Hardware/Panel/precadsr-panel/precadsr-panel-cache.lib create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/analogoutput_12mm.kicad_mod create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Potentiometer_Alpha_16mm_Long_Pin_Single_Vertical.kicad_mod create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Wall_wart_A-4118.kicad_mod delete mode 100644 Schematics/Luthers_Perfboard.pdf From dd8c61c34faaeb27b8a193b7a0410df7bb5b6b87 Mon Sep 17 00:00:00 2001 Subject: [PATCH] More traces and vias, and net links 06eccf7d9c added the once through idea with commentary by added the once through idea with commentary by added the once through idea with commentary by 496e3e3344 Correcting changed filename in .prl gets jiggy with PCB locator, 11 Pins per row (https://www.molex.com/pdm_docs/sd/430450201_sd.pdf), generated with kicad-footprint-generator Soldered wire connection, for 4 times 2 mm² wires, basic insulation, conductor diameter 0.65mm, outer diameter 1.5mm, size source Multi-Contact FLEXI-E 0.5 (https://ec.staubli.com/AcroFiles/Catalogues/TM_Cab-Main-11014119_(en)_hi.pdf), bend radius 3 times outer diameter, generated with kicad-footprint-generator ipc_gullwing_generator.py LQFP, 48 Pin (https://www.jedec.org/standards-documents/docs/mo-142-d variation DC), generated.

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