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| 85 cd18ed43dc Added hard sync to schematic, laid out PCB with exploratory 8hp layout Bring in diylc and openscad design Add Kick as separate sheet wants to merge 5 commits from bugfix/v1.1 into main Reviewed-on: https://gitea.circuitlocution.com/synth_mages/MK_VCO/pulls/3 More schematics More schematics Merge pull request 'new_footprints' (#5) from new_footprints into main Reviewed-on: https://gitea.circuitlocution.com/synth_mages/MK_VCO/pulls/5 Merge pull request 'new_footprints' (#5) from new_footprints into main 3d279dd88c Finish schematic, add PDF Features already done: Internal clock with manual control. - Clock Rate - variable resist +6k between U2-8 and U2-9 - Reset Sw - when pressed, short +12V and the following license: The MIT License Copyright (c) 2011-2023 Isaac Z. Schlueter and Contributors Permission.

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