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Traces "silk_line_width": 0.15, PCB initial layout, no traces "solder_mask_clearance": 0.0, PCB initial layout, no traces "solder_mask_clearance": 0.0, PCB initial layout, no traces }, More tweaks after pro review More tweaks after pro review "extra_units": "error", "global_label_dangling": "warning", "hier_label_mismatch": "error", "label_dangling": "error", "lib_symbol_issues": "warning", More tweaks after pro review Apply jlcpcb's design rules, small fixes for those Apply jlcpcb's design rules.

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