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BackWiring and increases risk of noise on power rails. Latest commits for file Schematics/schematic_bugs_v1.md Update Schematics/schematic_bugs_v1.md dcaec240831d28b722a7d7988287c76a1461e439 glide fix a5c5ff12ce18fecaaf346f973863d12bf361ac82 Notes from MK's PCB livestream - avoid non-circular holes in footprints whenever possible; some fabs charge more for ovals PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf) * [BOM](Docs/precadsr_bom.md) * [Build notes](Docs/build.md) How to apply smooth = 20; // How much horizontal space needed for left-hand and right-hand sub-panels left_panel_width = 12*3 + tolerance*2; // rib + half a jack col_right = width_mm - hole_dist_side, height - v_margin*2 - title_font_size; working_increment = working_height / (8+tolerance/3); // generally-useful spacing amount for vertical columns of stuff col_left = thickness * 1; //right_rib_x = width_mm - right_rib_thickness; Schematics/Dual_VCA.diy Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/C_Rect_L7.2mm_W2.5mm_P5.00mm_FKS2_FKP2_MKS2_MKP2.kicad_mod Normal file Unescape Hardware/PCB/precadsr_Gerbers/precadsr-PTH.drl Normal file View File # For PCBs designed using KiCad: http://www.kicad-pcb.org/ # Format documentation: http://kicad-pcb.org/help/file-formats/ # KiCad backups folders temp_* # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through.
- Connect Type073_RT02603HBLU pitch 5.08mm size 10.2x8.45mm^2 drill.
- 43160-1102, With thermal vias in pads, 3.
- Three position, dual pole triple.