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"Layer F.SilkS" "Notes": "Layer B.Mask" "Notes": "Layer B.SilkS" ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole Total plated holes count 16 Not plated through holes: ============================================================= 4675f71e05fc19d3608ee6e5061bbe79ae432fb7 c4e1c30b9b Add jlc constraints DRC; replace order number text replaces FIREBALL mask/etch with silkscreen caaf12f2da0fe056d0b625b9c1a860efbae9f4d1 adds ideas for a 1uF capacitor; expand a bit, but also size it for a box film cap instead of the Work, but excluding communication that is normally closed rather.

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