Labels Milestones
Back*~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 ============================================================= Total unplated holes count 0 Minor layout tweaks Minor layout tweaks Schematics/Fireball_VCO.pdf | Bin.
- Pitch=10.00mm, diameter=11.5mm, Supercapacitor, http://www.elna.co.jp/en/capacitor/double_layer/catalog/pdf/dx_e.pdf CP Radial series.
- -0.60387 0.705975 facet normal -2.113803e-001 -3.713470e-001.
- 2x12 1.00mm double row Through hole.
- SMD 2x23 2.00mm double row Through hole pin.