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Align panel to integer pseudo-origin, remove testing text, decrease title label font size to 9mm and align it precisely for repeatability b11a8d31874f2e074879a668b4f6eb5f32915bd6 Change transistor footprint to inline_wide, fix DRC ground plane Updates from real TL0x4s From 40588ba725f2f6c7240cc5d95c2a8af539e27e15 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Add some perfboard sections, power headers, teardrops checkpoint before getting really weird with WireIt A couple more minor clearance tweaks couple more GND-stitch vias From 77735c00cc3285131373f5cfc61b82eab5963d12 Mon Sep 17 00:00:00 2001 Latest commits for file Synth_Manuals/VALMORIFICATION+Build+and+BOM.pdf MK_VCO/Fireball/Fireball VCO saw wave core.circuitjs.txt Latest commits for file Docs/build.md footprint "Perfboard_3x12" (version 20221018) (generator pcbnew min_thickness 0.254) (filled_areas_thickness no (end -4.5 -4.4 (end 0 -0.127 (end 0 -10.287 (end 0 -5.207 (end 0 -10.287 (end 0 4.953 (end 0 -3.5 (end 0.261252 -0.735 (end -1.88 -0.98 (end 1.88 -0.98 (end -1.88 -0.98 (end -1.88 -0.98 (end -1.88 0.98 (end 1.88 -0.98 (end -1.88 0.98 (end -1 0.625 (end 1 0.625 (end 1 0.625 (end 1 -0.625 (end -1 -0.625 (end 1 0.625 (end 1 0.625 (end 1 -0.625 (end 1 -0.625 (end 1 -0.625 (end 1.

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