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Wires to run, so maybe not. It works this way. "pcb_color": "rgba(0, 0, 0, 0.000)", "schematic_color": "rgba(0, 0, 0, 0.000)", "schematic_color": "rgba(0, 0, 0, 0.000)", "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.25, "via_diameter": 0.8, "via_drill": 0.4, More tweaks after pro review "spice_external_command": "spice \"%I\"", More tweaks after pro review } ], "meta": { More tweaks after pro review 19116ba39d Apply jlcpcb's design rules, small fixes for those 7022ad9ddb couple more minor clearance tweaks couple more GND-stitch vias Latest commits for file Panels/dual_vca.scad T5 15.200mm 0.5984" (1 hole Total plated holes Total unplated holes count 16 Not plated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00 2001 Binary files /dev/null and b/Futura Heavy BT.ttf → Panels/Futura Heavy BT.ttf rename to Panels/Futura Heavy BT.ttf (grid_origin 84.5 17.5 Mark board for a single 2.5 mm² wires, reinforced insulation, conductor diameter 1.7mm, outer diameter 1.7mm, size source Multi-Contact FLEXI-E 0.75 (https://ec.staubli.com/AcroFiles/Catalogues/TM_Cab-Main-11014119_(en)_hi.pdf), bend radius 3 times 0.25 mm² wire, reinforced insulation, conductor diameter 0.9mm, outer diameter 3.6mm, size source Multi-Contact FLEXI-E 1.0 (https://ec.staubli.com/AcroFiles/Catalogues/TM_Cab-Main-11014119_(en)_hi.pdf), bend radius 3 times outer diameter, generated with kicad-footprint-generator Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-108-02-xx-DV-PE-LC, 8 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039300020_sd.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py LQFP, 100 Pin (JEDEC MO-153 Var BA https://www.jedec.org/document_search?search_api_views_fulltext=MO-153), generated with kicad-footprint-generator Molex Mini-Universal MATE-N-LOK, old.

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