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Add design rules for jlcpcb Add some perfboard sections, power headers, teardrops Add some perfboard sections, power headers, teardrops checkpoint before getting really weird with WireIt From 5ff3077e8252367b7eceb0b21b0803904b695d42 Mon Sep 17 00:00:00 2001 Subject: [PATCH] KiCad lib tables Hardware/Panel/precadsr-panel/fp-lib-table | 4 | 47k | Resistor | | | D 2 pin Molex connector 2.54 mm 2x5 | | C1 | 1 Hardware/lib/aoKicad | 1 | Conn_01x10 | Pin header, 2.54 mm, 1x7 | | | | | J7 | 1 C10, C14 too small for a single 1 mm² wire, basic insulation, conductor diameter 0.5mm, outer diameter 1.7mm, size source Multi-Contact FLEXI-E 0.1 (https://ec.staubli.com/AcroFiles/Catalogues/TM_Cab-Main-11014119_(en)_hi.pdf), bend radius 3 times outer diameter, generated with kicad-footprint-generator JST PUD series connector, B8B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator JST XH series connector, SM04B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator Hirose DF13 through hole, DF13-06P-1.25DSA, 6 Pins (https://www.molex.com/pdm_docs/sd/026605050_sd.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py VLGA, 4 Pin (http://www.vishay.com/docs/83510/tcmt1100.pdf), generated with kicad-footprint-generator JST VH series connector, B6P-VH-FB-B, shrouded.

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