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12 pin, exposed pad, thermal vias (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-12-11/ Infineon SO package 20pin, exposed pad - Ref http://pdfserv.maximintegrated.com/land_patterns/90-0349.PDF DFN, 10 Pin (http://www.ti.com/lit/gpn/tps63030#page=24), generated with kicad-footprint-generator JST ZE series connector, S13B-XASK-1 (http://www.jst-mfg.com/product/pdf/eng/eXA1.pdf), generated with kicad-footprint-generator Hirose DF13 through hole, DF11-18DP-2DSA, 9 Pins per row (http://www.molex.com/pdm_docs/sd/431600105_sd.pdf), generated with.

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