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Tweaks 0252301f35f8bebc5b9bb1af3f4a42193c706b15 More assembly notes cb59d1e9c06865f5bebe8c7ee0afa4859e0766b2 Update Schematics/schematic_bugs_v1.md more fixes glide fix a5c5ff12ce18fecaaf346f973863d12bf361ac82 re-re-remove the mysterious extra trace 5040873587dbb57684343269abab88d35cf7124b more fixes PSU/Synth Mages Power Word Stun Panel.kicad_pro Normal file View File 3D Printing/Pot_Knobs/Pot4.STL Executable file View File 3D Printing/Pot_Knobs/potentiometre_v3_1.5_merged.stl Normal file Unescape Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole Total plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes count 16 ============================================================= Total unplated holes count 16 ============================================================= Total unplated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes: merged pull request synth_mages/MK_VCO#3 created pull request 'pcb_finalization' (#1) from pcb_finalization into main v1 Final tweaks, version submitted to JLCPCB on 20240124 63579cf959 Add notes about UX component wiring 9f9f6acf76f746b4755da71c07bb656091774052 SMT updates 13c8bcac477b612d33e1b1cfe89a6f9adc0a8935 Adding SynthMages footprint library merged pull request synth_mages/MK_VCO#2 merged pull request synth_mages/MK_VCO#7 7#Cumulative fixes from v1.1 007cc05932 Checkpoint after tweaking footprints some more, starting over at 14hp main synth_tools/3D Printing/Cases/Eurorack Modular Case/20210926_092448.jpg Executable file View File Panels/futura medium condensed bt.ttf' Delete 'Panels/futura medium bt.ttf' From abc34915f3e0cdda969d62254e292cd8631b805a Mon Sep 17 00:00:00 2001 Latest commits for file Panels/FireballSpellVertSmall.png From bacdac34d747275148c56e8293dc209c2e326fe4 Mon Sep 17 00:00:00 2001 Subject: [PATCH] rm al panel Hardware/Panel/precadsr_panel_al/fp-lib-table | 4 .../PCB/precadsr_Gerbers/precadsr-B_Mask.gbr | 481 .../PCB/precadsr_Gerbers/precadsr-F_Paste.gbr | 15 .../precadsr-panel-SilkBottom.gbo | 799 .../precadsr-panel-drl_map.pdf | Bin 0 -> 169284 bytes create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/PinHeader_1x04_P2.54mm_Vertical.kicad_mod delete mode 100644 Hardware/Panel/precadsr_panel_al/precadsr_panel_al.sch create mode 100644 Schematics/Enlarge/Enlarge.kicad_pcb create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/PinHeader_1x03_P2.54mm_Vertical.kicad_mod create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Potentiometer_Alps_RK163_Single_Horizontal.kicad_mod create mode 100644 Hardware/Panel/precadsr_panel_al/precadsr_panel_al.pretty/precadsr-panel-holes.kicad_mod create mode 100644 Hardware/PCB/precadsr/Kosmo_panel.pretty/Kosmo_LED_Hole_NPTH.kicad_mod create mode 100644 Schematics/Fireball.kicad_sch create mode 100644 Schematics/SynthMages.pretty/IDC-Header_2x05_P2.54mm_Vertical_Fixed_Ground_Fill.kicad_mod create mode 100644 3D Printing/Rails/36hp_outie.stl | Bin 0 -> 92229 bytes Panels/FireballSpellSmall.png | Bin 0 -> 86371 bytes rename LUTHERS_VCO.diy => Schematics/LUTHERS_VCO.diy | 0 Schematics/MK_Schematic.png | Bin 12821 -> 0 bytes From 2d3c489f2acf0f8bdc9cf0fe8c2346d4d07472be Mon Sep 17 00:00:00 2001 Subject: [PATCH 18/18] Final revision; added custom DRC as project file tstamp 30cbcf99-eb70-4e15-8409-33e0ecd46602) Final revision; added custom DRC as project file tstamp 885d8854-95c7-40d1-bee9-0e598504ab1c) Final revision; added custom DRC as project file c4e1c30b9b Add jlc constraints DRC; replace order number text main MK_VCO/Panels/luther_triangle_vco_ .scad 283 lines 's take on FIREBALL VCO using AD&D 1e spell names in .../Panels/BLADE BARRIER.png.

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