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BackEmacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm.
- Normal 9.286611e-01 4.719780e-04 -3.709291e-01 vertex -9.041368e+01.
- Normal 1.575936e-001 2.757887e-001 9.482114e-001.