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- vias connect through the board, cross at 90° to minimize capacitance between traces vias connect through the PCB is used. In loop position, loop\nis connected to EP (http://www.aosmd.com/res/packaging_information/DFN5x6_8L_EP1_P.pdf 56-Lead Plastic Quad Flatpack No-Lead (LZ) - 2x3x0.9 mm Body [VDFN] (see Microchip Packaging Specification 00000049BS.pdf 44-Lead Plastic Shrink Small Outline (SSO/Stretched SO), see https://www.vishay.com/docs/84299/vor1142b4.pdf SSO Stretched SO SOIC 2.54 8-Lead Plastic Dual Flat No-Lead Package, Body 4.4x6.5x1.1mm, Pad 3.0x4.2mm, Texas Instruments EUS 5 Pin (https://www.jedec.org/sites/default/files/docs/MO-193D.pdf variant BA), generated with kicad-footprint-generator Mounting Hardware, inside through hole M3, height 9, Wuerth electronics 9774090482 (https://katalog.we-online.de/em/datasheet/9774090482.pdf), generated with kicad-footprint-generator XP_POWER IHxxxxD DIP DCDC-Converter XP_POWER IAxxxxS, SIP, (https://www.xppower.com/pdfs/SF_IA.pdf), generated with kicad-footprint-generator Molex Molex 0.30mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0130, 13 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator connector Molex Micro-Fit_3.0 top entry JST SH series connector, B13B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator Hirose FH12, FFC/FPC connector, FH12-53S-0.5SH, 53 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0694-9-81&productname=DF12C(3.0)-50DS-0.5V(81)&series=DF12&documenttype=2DDrawing⟨=en&documentid=0000994748), generated with kicad-footprint-generator Hirose series connector, 502386-0370 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator Samtec HLE.

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