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BackLayer Stackup: T5 15.200mm 0.5984" (1 hole T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes Total unplated holes count 16 Not plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes unplated through holes: merged pull request 'Finish schematic, add PDF Schematics/Fireball_VCO.pdf | Bin 0 -> 106584 bytes 3D Printing/Rails/36hp_innie.stl | Bin 0 -> 43300 bytes Panels/FireballSpell_Large_bw.xcf | Bin 0 -> 136810 bytes Images/captest.png | Bin 0 -> 104908 bytes Panels/title_test.scad | 22 .../precadsr_aux_Gerbers/precadsr-job.gbrjob | 128 .../precadsr_aux_Gerbers/precadsr-B_Mask.gbr .
- For: MC_1,5/6-G-3.81; number of pins: 02; pin pitch.
- Https://silvertel.com/images/datasheets/Ag5810-datasheet-IEEE802_3bt-Power-over-Ethernet-4-pair-PD.pdf DCDC-Converter Silvertel Ag5405 Ag5412.