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Back*~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: unplated through holes: ============================================================= d952ec97f3d5e1172c33dcefe438ee5d18f8d87d Start of LM13700 version to.
- 0.740028 -0.607324 0.288991 facet normal -0.06948 -0.7054 0.705395.
- HVSSOP, 8 Pin (https://www.jedec.org/system/files/docs/mo-187F.pdf variant AA), generated.
- Copies of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required.