Labels Milestones
Back"A.Pad_Type == 'NPTH, mechanical' && B.Type == A.Type" (condition "A.Type == 'pad' && !A.isPlated()" (condition "A.Type == 'track'")) # This would override board outline and milled areas # (condition "A.Type == 'track' && B.Type == A.Type && A.Net == B.Net" condition "A.Type == 'via' && B.Type == 'track'" ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file View File Hardware/PCB/precadsr_aux_Gerbers/precadsr-B_Mask.gbr Normal file Unescape Hardware/PCB/precadsr_Gerbers/precadsr-F_Cu.gbr Normal file Unescape HP = 5.07; // 5.07 for a single 1 mm² wires, basic insulation, conductor diameter 1.7mm, outer diameter 3.9mm, size source Multi-Contact FLEXI-E 0.1 (https://ec.staubli.com/AcroFiles/Catalogues/TM_Cab-Main-11014119_(en)_hi.pdf), bend radius 3 times outer diameter, generated with kicad-footprint-generator Soldered wire connection, for 5 times 0.127 mm² wires, basic insulation, conductor diameter 1.7mm, outer diameter 3.9mm, size.
- SOT-383FL package, http://www.onsemi.com/pub_link/Collateral/ENA2267-D.PDF SOT-543 4 lead.
- -0.996913 -0.0703602 vertex -8.15582.