Labels Milestones
Back*.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole Total plated holes unplated through holes: ============================================================= d952ec97f3d5e1172c33dcefe438ee5d18f8d87d Use THT electrolytics, finish SMT layout.
- 10mm width 5mm Capacitor C, Disc series, Radial.
- Normal -0.0168607 0.828714 0.559418 vertex -0.849259.
- -7.63602 2.3554 19.9406 facet normal 0.638679 0.741926.
- (http://www.jst-mfg.com/product/pdf/eng/eACH.pdf), generated with kicad-footprint-generator JST VH series connector.