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-0.100183 -0.114147 0.9884 vertex -5.2649 4.9518 6.88859 facet normal 0.772977 -0.634321 -0.011946 facet normal -0.634335 0.773058 0 facet normal -0.584885 -0.805014 0.0993115 facet normal -0.995186 0.0973393 0.0113559 vertex -1.07374 5.71699 21.335 facet normal -0.0962896 -0.976223 0.194209 facet normal -9.369149e-001 -4.172014e-003 3.495326e-001 vertex 4.064078e+000 8.060172e-001 2.480400e+001 facet normal 0.99044 0.0975476 0.0975398 vertex -8.83305 -1.69511 4.51215 facet normal 0.166294 0.21962 0.961308 facet normal -0.872204 -0.489142 0 vertex 9.99456 1.98804 0 facet normal -0.0992487 -0.989167 0.108159 facet normal 0.730673 -0.622319 0.280777 facet normal -0.343403 0.6852 0.64232 facet normal 0.643667 0.528237 0.553767 facet normal 0.734385 -0.39254 0.553707 facet normal 0.314572 -0.147387 0.937721 vertex -7.0162 -3.85359 19.9497 facet normal 0.918689 -0.264755 0.293113 vertex -4.98277 4.13938 7.73103 facet normal -3.562761e-001 6.107916e-001 7.071075e-001 facet normal 0.262755 0.257261 0.929934 vertex 4.99768 -5.42659 6.90571 facet normal -0.290358 -0.956918 0 facet normal 0.0189296 0.080194 0.9966 facet normal -5.270964e-06 -1.000000e+00 -4.340223e-07 vertex -1.042513e+02 9.665134e+01 1.109827e+01 facet normal -0.471404 -0.875976 0.102197 facet normal 0.528237 0.643667 0.553767 facet normal 4.784223e-001 8.781298e-001 0.000000e+000 vertex -6.672863e+000 -2.335454e+000 9.983999e+000 vertex 6.277050e+000 -3.351948e+000 1.747200e+001 facet normal 4.949278e-001 8.661241e-001 6.982482e-002 vertex -2.691560e+000 -3.117402e+000 2.470218e+001 facet normal 0.144955 -0.617512 0.77309 vertex 4.98874 -4.61842 7.03804 facet normal -0.295594 0.346112 0.89041 facet normal -2.880153e-004 -5.040268e-004 -9.999998e-001 ## Documentation: ### Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf) * [BOM](Docs/precadsr_bom.md) * [Build notes](Docs/build.md ## GitHub repository https://github.com/holmesrichards/precadsr Submodules Latest commits for file Panels/dual_vca.scad T5 15.200mm 0.5984" (1 hole) Total plated holes count 0 Minor layout tweaks merged pull request 'More schematics' (#3) from schematic by Eeschema 5.1.10-88a1d61d58~90~ubuntu20.04.1 **Component Count:** 77 **Component Count:** 76 Docs/precadsr_layout_back.pdf Normal file Unescape HP = 5.08; //If you want to socket the timing capacitors. ** Use only four (4) potentiometers, either 9 mm vertical pots. You can obtain a copy The MIT License Copyright (c) 2014 Mark Bates MIT License (MIT) Copyright (c) 2019 Cloudflare. All rights reserved. Copyright ©.

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