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D40f7ca1ca9e3e0f97e1dc4f553b9c659940a311 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Add note resulting from real TL0x4s re-re-remove the mysterious extra trace re-re-remove the mysterious extra trace Add notes about UX component wiring D36/R47 too close Testing before powering up: Clock In Normal - 1k to U2-8 (AND NOT short to U2-10 Clock Rate - variable resist +6k between U2-8 and U2-9 Reset Sw - when pressed, short +12V and Reset In socket Reset Socket to U3-3 = capacitor measurement roughly 15nF (has a resistor as well Once/Cont When in Cont mode shorts Casc Out normal to TP10, optional) - Casc out 2x Toggle Switches, 2pin: - Glide In - diode to U2-3 Clock In Normal - 1k to U2-8 (AND NOT short to U2-10 Clock Rate - variable resist +6k between U2-8 and U2-9 Reset Sw - when pressed, short +12V and the coarse knob to fix tuning range pushed tag v1.0 to synth_mages/MK_VCO Forget (and ignore) fp-info-cache file as it is safe to put the output jacks input_column = h_margin; bottom_row = v_margin + 12; row_1 = v_margin+12; Initial stab at a 10-step panel layout ideas out_row_1 = v_margin+12; row_2 = row_1 + vertical_space/7; cv_in_1a = [left_col, row_3, 0]; left_rib_x = thickness + 6 + tolerance; // left_panel_width = 16.5+16.5+10.5; //two knob, one jack, plus space between them right_panel_width = width_mm - h_margin; input_column = h_margin; col_right = width_mm - h_margin; col_left = thickness * 1.2; right_rib_x = width_mm - thickness*2; // draw panel, subtract holes // label the whole thing? // surface("FIREBALL VCO.png", center=true, invert=false); Binary files /dev/null and b/Schematics/Luthers_VCO_schematic.pdf differ main synth_tools/Schematics/SynthMages.pretty/PinSocket_1x02_P2.54mm_Vertical.kicad_mod 42 lines synth_tools/PCB Notes.txt 17 lines e8295830c4 STLs, 10hp version, others schematics thickness=2; label_inset_height = thickness-1; module label(string, size=4, halign="center") { PSU/Synth Mages Power Word Stun Panel.kicad_pcb Normal file View File 3D Printing/Cases/Eurorack Modular Case/DSC03766.JPG Executable file View File Hardware/PCB/precadsr_Gerbers/precadsr-B_Mask.gbr Normal file Unescape Hardware/PCB/precadsr_aux_Gerbers/precadsr-F_Cu.gbr Normal file Unescape The laws of most jurisdictions throughout the world based on http://www.latticesemi.com/view_document?document_id=213 Lattice caBGA-756, ECP5 FPGAs, 27.0x27.0mm, 756 Ball, 32x32 Layout, 0.8mm Pitch, https://www.micron.com/-/media/client/global/documents/products/data-sheet/dram/ddr3/4gb_ddr3l.pdf#page=24 FBGA-78, 10.5x8.0mm, 78 Ball, 9x13 Layout, 0.8mm Pitch, https://www.infineon.com/cms/en/product/packages/PG-LFBGA/PG-LFBGA-292-11/ LFBGA-100, 10x10 raster, 8x8mm package, 0.5mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=267, NSMD pad definition Appendix A BGA 676 1 FF676 FFG676 FFV676 Kintex-7 and Zynq-7000 BGA, 15x15 grid, 13x13mm package, pitch 0.4mm; see section 6.6 of http://www.st.com/resource/en/datasheet/DM00273119.pdf X1-WLB0909, 0.89x0.89mm, 4 Ball, 2x2 Layout, 0.5mm Pitch, https://www.st.com/resource/en/datasheet/stm32mp151a.pdf ST LFBGA-448, 18.0x18.0mm, 448 Ball, 22x22 Layout, 0.8mm Pitch, http://www.latticesemi.com/view_document?document_id=213 Analog Devices KS-4, http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/sc70ks/ks_4.pdf Analog Devices (Linear Tech), 133-pin LGA uModule, 15.0x15.0x4.32mm, https://www.analog.com/media/en/technical-documentation/data-sheets/4637fc.pdf NXP LGA, 8 Pin (http://ww1.microchip.com/downloads/en/AppNotes/S72030.pdf), generated with kicad-footprint-generator.

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