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(Mono / TS), Switched T Pole (Normalling Audio Jack, 2 Poles (Mono / TS), Switched T Pole (Normalling) Schottky Barrier Rectifier Diode, DO-41 | | | | | | | | | Tayda | A-1624 or A-2969 | | | | | Tayda | A-1955 | | | | | R9, R11, R13 | 3 | A1M | Potentiometer | | | | | | | S2 | 1 | 2_pin_Molex_header | KK254 Molex header 2.54 mm spacing | | | | 4 .../PCB/precadsr_Gerbers/precadsr-F_Cu.gbr | 4 README.md | 4 b96c823428 Delete '3D Printing/AD&D 1e spell names in Filmoscope Quentin/Panels/MAGIC MISSILE VCF.png' f707877a83c92d22bdfed3b6bc7a14bba9e25bab Delete '3D Printing/AD&D 1e spell names in Filmoscope Quentin' Delete '3D Printing/AD&D 1e spell names in Filmoscope Quentin/Panels' 16700 bytes .../SPIDER CLIMB.png | Bin 0 -> 11692 bytes .../Panels/HOLD PORTAL.png | Bin 0 -> 9479 bytes main ENV/.gitignore 32 lines usegerberextensions false) (usegerberattributes false) (usegerberadvancedattributes false) (creategerberjobfile false) New KiCad version; non Al panel Gerbers # Netlist files (exported from Pcbnew # Exported BOM files *.xml *.csv # KiCad backups folders temp_* # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) Total plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) T5 15.200mm 0.5984" (1 hole T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes count 16 Not plated through holes are merged with plated holes count 16 Not plated through holes are merged with plated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes: ============================================================= e49f4ab127dc081ee1c77dd21e80d128628a1152 c9e81f0cc630cea052574ce7c50b3e82145bb626 Image of caxia score 531ebcae92 Add html test version b22080a808 More experimentation with panel alignment before printing Messing around with panel title fonts Futura BT.

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