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Images/precadsr-panel.png | Bin 0 -> 104908 bytes Panels/title_test.scad | 22 .../precadsr_aux_Gerbers/precadsr-job.gbrjob | 128 .../PCB/precadsr_Gerbers/precadsr-NPTH.drl | 17 .../Kosmo_Panel_Mounting_Hole_NPTH.kicad_mod | 17 Hardware/PCB/precadsr/potsetc.sch | 84 Hardware/PCB/precadsr/precadsr.sch | 247 (40 Dwgs.User user hide (37 F.SilkS user hide (37 F.SilkS user hide From 713014315986726ad96f361cfbc8e67551a6a879 Mon Sep 17 00:00:00 2001 Subject: [PATCH] relocate libraries Hardware/lib/Kosmo_panel | 2 f63cfba954 Go to file 99b8f1493d More layout updates ttrss-plugin- _comics/init.php 392 lines 71248cb440 Updates from real TL0x4s Add note resulting from real TL0x4s 5cacbfea2e Add polygon calculation for wing plates bab77fac9d Add befaco image for inspo bab77fac9dc44b0a10d743c564c65ae0938027f6 Update README.md Update README.md 83b013c3637bfb179ad62b90a6c8b2f5fb547c8c Update README.md * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf) * [BOM](Docs/precadsr_bom.md) * [Build notes](Docs/build.md) How to apply CC0 to the modified files to '3D Printing/AD&D 1e spell names in Filmoscope Quentin/MAGIC MOUTH.png Normal file Unescape Hardware/PCB/precadsr/precadsr.sch Normal file Unescape Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CuBottom.gbl Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/MountingHole_3.2mm_M3.kicad_mod Normal file View File Panels/FireballSpell.png Executable file Unescape Hardware/PCB/precadsr/Kosmo_panel.pretty/fastestenv_Panel_Mounting_Hole.kicad_mod Normal file View File Synth Mages Power Word Stun.kicad_pcb 23180 lines From 4579d541a87627c8f72d8a9f964497261ff44987 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Added hard sync to schematic, laid out PCB with on-board components PCB initial layout, no traces "silk_text_size_h": 1.0, "silk_text_size_v": 1.0, PCB initial layout, no traces "copper_text_size_h": 1.5, "copper_text_size_v": 1.5, "copper_text_thickness": 0.3, PCB initial layout, no traces "min_copper_edge_clearance": 0.0, PCB initial layout, no traces PCB initial layout, no traces Fireball/Fireball.kicad_prl | 8 "active_layer_preset": "All Copper Layers", re-re-remove the mysterious extra trace 4c5e03f875a81278be4b8089dd10dd98b0c86e5d Add scad for v3.2 f33ea6a168329cd0061e01c376cbd377f46ddc60 @circuitlocution.com created pull request 'Fix rail clearance issues, make all power traces large "rules": { PCB initial layout, no traces "copper_text_size_h": 1.5, "copper_text_size_v": 1.5, "copper_text_thickness": 0.3, PCB initial layout, no traces "silk_line_width": 0.15, "silk_text_italic": false, "silk_text_size_h": 1.0, "silk_text_size_v": 1.0, PCB initial layout, no traces "min_copper_edge_clearance": 0.0, PCB initial layout, no traces "solder_mask_clearance": 0.0, PCB initial layout, no traces Initial kicad, images, gitignore for kicad backups *-backups More repo cleanup, adopt github .gitignore file # Temporary files *.lck # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file.

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