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BackLines }, "silk_line_width": 0.15, PCB initial layout, no traces Using the Precision ADSR build notes | C7, C12, C13 | 1 | 4.7 uF | Polarized capacitor | | | Tayda | A-4349 | | J2 | 1 nF | Unpolarized capacitor | | | R1, R2, R23, R24 | 4 .../precadsr_Gerbers/precadsr-Edge_Cuts.gbr | 4 .../precadsr-Edge_Cuts.gbr | 16 .../precadsr_aux_Gerbers/precadsr-F_Cu.gbr | 580 .../precadsr_aux_Gerbers/precadsr-F_Mask.gbr | 185 .../precadsr_aux_Gerbers/precadsr-B_Paste.gbr | 4 | 100 nF | Unpolarized capacitor | | S2 | 1 Fireball/Fireball.kicad_pcb | 7889 Fireball/Fireball.kicad_sch | 64 Fireball/fp-info-cache | 36 ...gson_DG301_1x03_P5.00mm_Vertical.kicad_mod | 63 3D Printing/Panels/Radio_shaek_standoff.stl create mode 100644 Schematics/SynthMages.pretty/POT_2_PIN_Header.kicad_mod create mode 100644 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-PasteBottom.gbp create mode 100644 Hardware/Panel/precadsr-panel/precadsr-panel.pretty/Bigger_Push_Switch_Hole.kicad_mod create mode 100644 Docs/precadsr_layout_back.pdf (grid_origin 97.28 88.9
- Hw) { holes .
- 0.768773 0.108219 facet normal -9.402140e-01 -3.405843e-01.
- 1.151572e+01 vertex -1.073615e+02 9.695134e+01 1.152727e+01.
- 6.451590e-01 3.338815e-04 vertex -1.032505e+02 1.030635e+02 1.055000e+01.