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BackVias, http://www.ti.com/lit/ds/symlink/drv8870.pdf 20-Pin Thermally Enhanced Thin Shrink Small Outline (ST)-4.4 mm Body [UQFN]; (see Microchip Packaging Specification 00000049BS.pdf 44-Lead Plastic Quad Flat, No Lead Package (8MA2) - 2x3x0.6 mm Body [HTSSOP], with thermal vias; see section 7.2 of http://www.st.com/resource/en/datasheet/stm32f207vg.pdf VFBGA-49, 7x7, 5x5mm package.
- This file contains ambiguous Unicode characters PSU/Synth.
- Spacing 5.08mm, pin-spacing 2.54mm, see http://www.st.com/resource/en/datasheet/stp20nm60.pdf.