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Back*-backups */fp-info-cache *.kicad_prl *.sch-bak *~ _autosave-* *.tmp *-save.pro *-save.kicad_pcb fp-info-cache # Autorouter files (exported from Eeschema *.csv *.lck ########################## # Additional ignored # KiCad backups folders temp_* # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes count 16 Latest commits for file .gitattributes | 2 Examples/EG_MANUAL.pdf | Bin 9479 -> 14135 bytes caixa_sr2.png | Bin 0 -> 31010 bytes Panels/label_test.stl | Bin 0 -> 10724 bytes .../Panels/MAGIC MISSILE VCF.png | Bin 0 -> 11930 bytes create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/analogoutput_12mm.kicad_mod create mode 100644 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-SilkTop.gto create mode 100644 Docs/precadsr_layout_back.pdf (grid_origin 97.28 88.9
- Vertex 1.701279e+000 -4.959860e+000 2.484855e+001 facet normal -4.282516e-16.
- -2.3554 19.9406 facet normal 0.920058.
- AcDbLinetypeTableRecord 2 BYLAYER 70 0.
- SMD 2x36 1.27mm double row Through.