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Raster, 4.539x5.849mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32f031k6.pdf WLCSP-25, 5x5 raster, 2.133x2.070mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/DM00284211.pdf WLCSP-104, 9x12 raster, 4.095x5.094mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32f303r8.pdf WLCSP-49, 7x7 raster, 2.965x2.965mm package, pitch 0.5mm; see section 48.2.4 of http://ww1.microchip.com/downloads/en/DeviceDoc/DS60001479B.pdf WLCSP-81, 9x9, 0.4mm Pitch, https://www.st.com/resource/en/datasheet/stm32g0b1ne.pdf#page=136 ST WLCSP-64, ST die ID 495, 4.4x4.38mm, 100 Ball, 10x10 Layout, 0.4mm Pitch, https://www.st.com/resource/en/datasheet/stm32g483me.pdf ST WLCSP-81, ST die ID 469, 4.02x4.27mm, 81 Ball, 9x9 Layout, 0.4mm Pitch, YFF0006, NSMD pad definition Appendix A Virtex-7 BGA, 42x42 grid, 42.5x42.5mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=271, ttps://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=281, https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=82, NSMD pad definition Appendix A BGA 238 0.5 CPG238 Spartan-7 BGA, 15x15 grid, 13x13mm package, pitch 0.5mm (http://www.analog.com/media/en/package-pcb-resources/package/56702234806764cp_24_3.pdf, http://www.analog.com/media/en/technical-documentation/data-sheets/ADL5801.pdf LFCSP VQ, 24 pin, exposed pad: 4.5x8.1mm, (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-12-9/ Infineon PG-DSO 12 pin, exposed pad: 4.5x8.1mm, (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-12-9/ Infineon PG-DSO 12 pin, exposed pad, 7x7mm body (http://www.analog.com/media/en/technical-documentation/data-sheets/AD7951.pdf, http://www.analog.com/en/design-center/packaging-quality-symbols-footprints/symbols-and-footprints/AD7951.html LFCSP-WD, 8 Pin (https://media.digikey.com/pdf/Data%20Sheets/Rohm%20PDFs/BD9G341EFJ.pdf), generated with kicad-footprint-generator Molex KK-254 Interconnect System, old/engineering part number: 09-65-2078, 7 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator Molex 734 Male header (for PCBs); Angled solder pin 1 (so is open or ground). Part of speed \nswitch mod (0 F.Cu signal (31 "B.Cu" signal (32 B.Adhes user (33 F.Adhes user (34 B.Paste user (35 "F.Paste" user (36 B.SilkS user (37 F.SilkS user (38 B.Mask user (39 "F.Mask" user (40 Dwgs.User user (41 Cmts.User user (42 Eco1.User user hide (48 B.Fab user hide (42 Eco1.User user (43 Eco2.User user (44 Edge.Cuts user (45 Margin user (46 "B.CrtYd" user "B.Courtyard" (47 "F.CrtYd" user "F.Courtyard" (48 "B.Fab" user (49 "F.Fab" user (aux_axis_origin 0 0 Y N 1 F N DEF SW_Coded_SH-7080 SW 0 40 0.0 0 LTYPE 5 15 330 5 100 AcDbSymbolTableRecord 100 AcDbLinetypeTableRecord 2 BYLAYER 70 0 3 vertex 3.44415 -8.31492 0 vertex -2.42184 2.42184 18.1498.

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