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Back[PATCH] checkpoint after roughing out middle PCB Binary files /dev/null and b/Images/precadsr-panel.png differ From f50bb0019af1e23a68a47e827989c11465d543f5 Mon Sep 17 00:00:00 2001 main MK_VCO/.gitattributes 3 lines sym_lib_table New KiCad version; non Al panel Gerbers # Netlist files (exported from Eeschema *.csv *.lck ########################## # Additional ignored # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ Initial version \#* New KiCad version; non Al panel Gerbers # Netlist files (exported from Eeschema *.csv *.lck ########################## # Additional ignored # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes count 16 Not plated through holes are merged with plated holes count 16 Not plated through holes are merged with plated holes count 16 Not plated through holes: .
- 0.0727061 -0.0568312 0.995733 vertex 7.13918 0.0610838 6.87866 vertex.
- 6.164997e-01 vertex -1.083797e+02 9.725134e+01 1.119586e+01 facet normal -0.991524.