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Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes count 16 ============================================================= Total unplated holes count 16 Latest commits for file Synth_Manuals/VALMORIFICATION+Build+and+BOM.pdf MK_VCO/Fireball/Fireball VCO saw wave core.circuitjs.txt 90 lines From 978eb1d01f159b84c8992f501a13cc201d7f141a Mon Sep 17 00:00:00 2001 Subject: [PATCH] more fixes more fixes a5c5ff12ce18fecaaf346f973863d12bf361ac82 re-re-remove the mysterious extra trace 5040873587dbb57684343269abab88d35cf7124b Update Schematics/schematic_bugs_v1.md 5040873587dbb57684343269abab88d35cf7124b Update Schematics/schematic_bugs_v1.md Update Schematics/schematic_bugs_v1.md b2f0340111348a8deafde0ffe244939fe4eeb6b7 add pic Schematics/bad_trace_v1.jpeg | Bin 0 -> 317907 bytes Images/PXL_20210831_004139245.jpg | Bin 0 -> 36336 bytes create mode 100644 Hardware/PCB/precadsr_Gerbers/precadsr-F_SilkS.gbr create mode 100644 Schematics/SynthMages.pretty/PinSocket_1x02_P2.54mm_Vertical.kicad_mod create mode 100644.

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