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BackF.Cu" "Notes": "Layers L1/L2" "Notes": "Layer B.SilkS" ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole Total plated holes count 16 Latest commits for file Images/precadsr-panel-holes.png 972d8b1e07 adds front panel to integer pseudo-origin, remove testing text, decrease title label font so we don't lose it 734cf9b18c Add the label font size to 9mm and align it precisely for repeatability Change transistor footprint to inline_wide, fix DRC ground plane spokes can be generous with this design is the license create a new version .../Bigger_Push_Switch_Hole_NPTH.kicad_mod | 13 ...6.3mm_D2.5mm_P10.16mm_Horizontal.kicad_mod | 39 ...L6.3mm_D2.5mm_P7.62mm_Horizontal.kicad_mod | 39 .../ao_tht.pretty/Rotary_Switch.kicad_mod | 38 .../SOT-23_Handsoldering.kicad_mod .
- 0.586535 -0.665684 0.461347 facet normal.
- 156.1525 129.5 (end 160.35 131.75 (end 162.9025.
- SmallPads 8-lead though-hole mounted DIP package, row.