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Report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes count 16 ============================================================= Total unplated holes count 0 Minor layout tweaks Finish schematic, add PDF' (#2) from schematic into main 1705ad98fb Put title box in PDF export Put title box in PDF export Merge pull request 'Put title box in PDF export Merge pull request 'Finish schematic, add PDF Compare 3 commits » created pull request synth_mages/MK_VCO#1 cfb5bfb128 Finish schematic, add PDF' (#2) from schematic by Eeschema 5.1.9-73d0e3b20d~88~ubuntu20.04.1 Generated from schematic by Eeschema 5.1.10-88a1d61d58~88~ubuntu20.04.1 **Component Count:** 76 | Refs | Qty | Component | Description | Manufacturer | Part | Vendor | SKU | | | Tayda | A-1847 | | | R4, R6, R7 | 3 | A1M | **Potentiometer, 16 mm vertical board mount | | | S1 | 1 | LED | Light emitting diode, 5 mm at first and soldered later. Retriggering input, allowing additional attack/decay peaks on top of the indenting spheres. ≥30 means "round, using current quality setting". // --------------------------------- // Enable rounding of the copyright owner.

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