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Back# LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 Not plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) Total plated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file Unescape ; DRILL file {KiCad 5.1.10-88a1d61d58~90~ubuntu20.04.1} date Thu Aug 12 15:59:21 2021 ac58a9eaed checkpoint after roughing out middle PCB Update to 7.0, slider footprint cb3a50e19a More tweaks after pro review Apply jlcpcb's design rules, small fixes.
- -3.176384e-001 -1.414236e-003 9.482109e-001 vertex.
- 7.575048e-001 4.886913e-001 facet normal.
- DPAK-3 TO-252-3 SOT-428 TO-252-2, tab.
- -9.527803e-01 3.036606e-01 0.000000e+00 facet normal 0.0810354 0.083183.
- 26-60-4040, 4 Pins per row.