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Back4.784807e-07 -1.000000e+00 -5.637708e-07 facet normal -1.458075e-15 -1.388642e-15 -1.000000e+00 vertex -1.103843e+02 9.755134e+01 1.512829e+01 facet normal -0.471394 0.881923 0 vertex 2.42705 1.76336 0 vertex -8.31492 -3.44415 3.82299 facet normal -0.0979739 0.995118 -0.0119198 facet normal 0.877714 -0.469149 0.0975597 facet normal 5.356989e-002 9.985641e-001 0.000000e+000 facet normal -2.880153e-004 -5.040268e-004 -9.999998e-001 ## Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf * [How to use](Docs/use.md 96f746fa2d Final tweaks, version submitted to JLCPCB on 20240124 v1.0 Add CV in to pause the sequence. Probably can't do, or impractical: CV-controlled clock. Presumably the CV in to pause the clock From 96e9dd144019309f3e33f1daf66ec448c4e2d994 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Update current state of project. Add correct footprints to fireball From e9734fb673e2df8488e62f7bd94252034b048666 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Use THT electrolytics, finish SMT layout, try on quentin font for size Schematics/Dual_VCA_with_cv2_OTA.diy Normal file View File Merge pull request 'More schematics' (#3) from schematic into main ... Add jlc constraints DRC; replace order number text Fireball/Fireball_panel.kicad_pcb | 3 | 2N3904 | 0.2A Ic, 40V Vce, Small Signal NPN Transistor, TO-92"/>