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PHB. # Exported BOM files *.xml *.csv # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes) T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes count 16 Not plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole Total plated holes unplated through holes: ============================================================= 744b72ef7e0d94fccfae99ec3cb3514981ac4616 77735c00cc3285131373f5cfc61b82eab5963d12 Update README.md 5505000471ab249f70d985a8f814bce077fb47b2 Update README.md 83b013c3637bfb179ad62b90a6c8b2f5fb547c8c Update README.md 2cb8e5eaf679e30139948d8744800b04487466fc updated C5 footprint & tracing; schematic annotation updated C5 footprint & tracing; schematic annotation Add 55k-ish resistor to coarse knob to fix tuning range Add 55k-ish resistor to coarse knob to fix tuning range 's notes on updating the fireball for rev 2 beta README.md | 3 | 2N3904 | 0.2A Ic, 40V Vce, Small Signal NPN Transistor, TO-92 | | | Tayda | A-559 | | | C12 | 2 | 1M | Resistor | | | R14 | 1 | Conn_01x10 | Pin socket, 2.54 mm, 1x10 Pin socket, 2.54 mm, 1x4 | | AR Path="/607F01E7" Ref="R?" Part="1" AR Path="/60A9C081" Ref="R?" Part="1" AR Path="/607ED812/60800A40" Ref="R113" Part="1" AR Path="/607ED812/60B16110" Ref="J8" Part="1" AR Path="/607ED812/60A9C096" Ref="R9" Part="1" AR Path="/607ED812/609384DB" Ref="#FLG0102" Part="1" AR Path="/609384DB.

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