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| R25, R27, R29 | 3 | 2N3904 | 0.2A Ic, 40V Vce, Small Signal NPN Transistor, TO-92 | | R30 | 1 4 files changed, 623 deletions(- delete mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Arduino_Nano.kicad_mod create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Molex_KK-254_AE-6410-03A_1x03_P2.54mm_Vertical.kicad_mod create mode 100644 Hardware/Panel/precadsr_panel_al/fp-lib-table create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Power_Header.kicad_mod delete mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/PinHeader_1x03_P2.54mm_Vertical.kicad_mod delete mode 100644 3D Printing/Pot_Knobs/scaled_french_pot.mix Normal file View File Schematics/Kassutronics_Slope_Build_Docs_2.0A.pdf Normal file Unescape Schematics/SynthMages.pretty/PinSocket_1x03_P2.54mm_Vertical.kicad_mod Normal file View File 3D Printing/Cases/Eurorack Modular Case/EuroRack_Case_Power.stl Executable file Unescape Hardware/PCB/precadsr_Gerbers/precadsr-job.gbrjob Normal file View File Datasheets/2N3903-Motorola.pdf Executable file View File Panels/FireballSpell_Large.webp Executable file Unescape Fireball/Fireball.kicad_pro Normal file Unescape Hardware/PCB/precadsr/Kosmo_panel.pretty/Kosmo_Panel_Mounting_Hole_NPTH.kicad_mod Normal file View File Schematics/Baby8_Part4_Cascading.pdf Normal file View File 3D Printing/Cases/Eurorack 2-Row/eurorack_2row_power_supply_base.skp Executable file Unescape Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes count 16 Not plated through holes: unplated through holes: ============================================================= c9e81f0cc630cea052574ce7c50b3e82145bb626 Image of caxia score 531ebcae92 Add html test version Samurai Latest commits for file Synth_Manuals/Kassutronics_Slope_Build_Docs_2.0A-1.pdf 4fd9d8b7bf Delete 'Panels/Futura XBlk BT.ttf' e825437e5d Upload files to '3D Printing/AD&D 1e spell names in Filmoscope Quentin/Panels/PRISMATIC SPHERE.png' Delete '3D Printing/AD&D 1e spell names in Filmoscope Quentin/Panels/HOLD PORTAL.png' Delete '3D Printing/AD&D 1e spell names in Filmoscope Quentin/Panels/PRISMATIC SPHERE.png' Schematic updates tstamp 279a77ec-bb4c-42b3-9906-0ade47adceea) ) Schematic updates tstamp fba516e7-1049-45b0-8dba-0ae3b2bc2d6f) ) Schematic updates 13c8bcac477b612d33e1b1cfe89a6f9adc0a8935 Adding SynthMages footprint library Notes from MK's PCB livestream Footprints: - avoid non-circular holes in footprints whenever possible; some fabs charge more for ovals avoid non-circular holes in footprints whenever possible; some fabs charge more for ovals - make power connection traces larger; MK uses a CA3080 OTA, an expensive and rare chip these days ($3/ea on amazon, maybe fakes) VCA MK's VCA Probably a straightforward build: one op-amp, four transistors and some example modules Envelope/Envelope.kicad_pcb | 2 Panels/futura medium bt.ttf Normal file Unescape .

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