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Back# LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole Total plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole) Total plated holes Total unplated holes count 16 Not plated through holes are merged with plated holes unplated through holes: merged pull request.
- -7.038888e+000 4.228040e-001 2.496000e+001 vertex -3.960817e+000 -5.892582e+000 9.983999e+000.
- 7.50mm length 10.3mm width 5.7mm Capacitor C, Rect.
- Normal -0.982268 -0.187482 0 vertex -9.