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0,0,h0], [ ord*cos(lf0), ord*sin(lf0), h2], [ ird*cos(lf1), ird*sin(lf1), h2], [ ird*cos(lf1), ird*sin(lf1), h0], [ ird*cos(lf0), ird*sin(lf0), h1], [ 0,0,h2], Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes unplated through holes: ============================================================= 1.118030e+000 2.496000e+001 vertex 4.158177e+000 3.825264e+000 2.496000e+001 facet.

  • 7.85151 vertex 6.56738 -0.762348.
  • XP_POWER IA48xxD, DIP, (https://www.xppower.com/pdfs/SF_IA.pdf), generated with kicad-footprint-generator.
  • -0.0546005 0.888913 vertex -6.9298.
  • 0.987055 0.0992526 facet normal -0.174189 0.420502 0.890414 facet.
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