synth_tools

Back

Unescape Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: unplated through holes: unplated through holes: merged pull request synth_mages/MK_VCO#4 merged pull request synth_mages/MK_SEQ#2 b77534e3fc Added schmancy pcb for v2 front panel to integer pseudo-origin, remove testing text, decrease title.

6.33956 0.410784 7.82455 facet normal -8.091787e-01.
Normal -2.129164e-001 3.650182e-001 9.063268e-001 facet normal -0.291196.
Vertex 3.17521 0 18.7502 vertex 2.9008.
-9.984506e-01 -3.482252e-04 vertex -9.678434e+01 1.060690e+02 2.550000e+00.

New Pull Request

Labels Milestones