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Layer Stackup: T5 15.200mm 0.5984" (1 hole) Total plated holes unplated through holes: unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes count 0 Minor layout tweaks merged pull request 'Put title box in PDF export Merge pull request 'Finish schematic, add PDF | J6 | 1 | TL074 | Quad Low-Noise JFET-Input Operational Amplifiers, DIP-14/SOIC-14"/> X="5.35" y="3.2"/> Starts interfering with the Work and reproducing the. New Pull Request

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