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BackLayout Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: unplated through holes: unplated through holes.
- See https://diotec.com/tl_files/diotec/files/pdf/datasheets/kbpc600.pdf Single phase bridge rectifier, https://www.bourns.com/docs/Product-Datasheets/CD-DF4xxSL.pdf Surface.
- 5.957504e-001 vertex 5.100596e+000 2.921475e+000 2.484593e+001.
- Ac dc rac01xxgb rac01-05sgb rac01-12sgb recom power ac.
- Pitch 0.5mm UFBGA-64, 8x8 raster.
- 0.866027 1.12546e-07 facet normal -0.471366 -0.881857 -0.0118779.