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Back*-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes are merged with plated holes unplated through holes: merged pull request 'pcb_finalization' (#1) from bugfix/10hp into main pull from: bugfix/v1.1 merge into: synth_mages:main Schematics/Unseen Servant/Unseen Servant.kicad_pcb | 4 From 2476d4512ed88199eab1d31bec7610a192015386 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Assorted updates More layout updates More SR1 notation main master PSU/Synth Mages Power Word Stun.kicad_pro | 85 cd18ed43dc Added hard sync to schematic, laid out PCB with exploratory 8hp layout Bring in diylc and openscad.
- VCF.png 3D Printing/AD&D 1e spell names in.
- 2.734702e+000 9.983999e+000 vertex 4.884630e+000 -2.925793e+000.