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-7.31983 7.07423 vertex 5.54018 4.83492 6.98312 vertex 7.16112 0.632185 7.08096 vertex 4.57828 -5.3829 7.06725 vertex -5.45272 -4.78839 6.97207 facet normal -2.94821e-05 -0.956933 -0.290308 vertex 1.31069 3.16429 18.1498 facet normal -0.258276 0.111525 0.959612 facet normal -0.471406 -0.881916 0 facet normal 0.262751 0.491602 0.830234 facet normal -0.00043693 0.116114 0.993236 vertex -6.9148 -0.996058 7.89166 facet normal 0.000000e+00 -9.486858e-15 1.000000e+00 facet normal -4.533805e-002 9.989717e-001 0.000000e+000 vertex 5.055779e+000 -2.918668e+000 2.464800e+001 facet normal -0.000195511 0.116119 0.993235 facet normal -2.561793e-15 -1.455906e-15 -1.000000e+00 facet normal -0.0972815 -0.989353 0.108241 facet normal -2.880153e-004 -5.040268e-004 -9.999998e-001 ## Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf) * [BOM](Docs/precadsr_bom.md) * [Build notes](Docs/build.md ## GitHub repository ## Git repository ### Git repository From 40ce306867b3d353457e134a232ee65f5767bece Mon Sep 17 00:00:00 2001 Subject: [PATCH 05/18] Added input resistor for sync; placed everything on PCB Added hard sync to schematic, laid out PCB with exploratory 8hp layout Add VCA shaek layout These branches are equal. From c58f541d7e93b3fa0676ab29736db865cc42ef96 Mon Sep 17 00:00:00 2001 Subject: [PATCH] updated README.md README.md | 2 pin 0.6x1mm 0.375mm height package, https://www.ti.com/lit/ml/mpss034c/mpss034c.pdf, https://www.ti.com/lit/ds/symlink/tpd6e05u06.pdf USON, 14 Pin (JEDEC MO-153 Var CC https://www.jedec.org/document_search?search_api_views_fulltext=MO-153), generated with kicad-footprint-generator ipc_noLead_generator.py DC6 Package; 6-Lead Plastic DFN (2mm x 2mm) (see Linear Technology DFN_14_05-08-1708.pdf DFN14, 4x4, 0.5P; CASE 505AB (see ON Semiconductor 932BB.PDF 144-Lead Plastic Thin Shrink Small Outline No-Lead http://www.ti.com/lit/ml/mpds176e/mpds176e.pdf Plastic Small Outline (SS)-5.30 mm Body [SOIC.

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