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Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes are merged with plated holes count 16 Not plated through holes: merged pull request 'Put title box in PDF export Merge pull request synth_mages/MK_VCO#5 Merge pull request synth_mages/MK_VCO#5

everything done as a full circle. NOT IMPLEMENTED YET. Quality = "preview.

= 5*1; DivotDepth = 1.5*1.
Impractical: - CV-controlled clock.

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