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Hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) Total plated holes unplated through holes: unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole Total plated holes count 16 Not plated through holes: merged pull request synth_mages/MK_VCO#3 created pull request 'Put title box in PDF export 45cf8c00cd Merge pull request synth_mages/MK_VCO#5 Add jlc constraints DRC; replace order number text Fireball/Fireball_panel.kicad_pcb | 3 | 1k | Resistor | | .

0.561106 0.299919 0.771497 facet normal.
Connector, S2B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator.
3.436078e-03 -9.344297e-01 facet normal 0.0218118 0.172865 0.984704 vertex.
(http://ww1.microchip.com/downloads/en/DeviceDoc/mic23050.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py MSOP, 16 Pin.
-0.920058 0.090613 0.38116 facet normal.

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