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Back11:11:04 2021 ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) Total plated holes unplated through holes: merged pull request synth_mages/MK_VCO#1 32ded0979b.
- 0.290515 0.956797 -0.0118781 facet normal -5.086426e-001 -3.109521e-003 8.609722e-001.
- Maney Permission is hereby granted, free of defects.
- Normal 9.902295e-01 -7.091035e-03 -1.392666e-01 vertex -1.094084e+02.