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BackDistance 25mm 9-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 4.9399999999999995mm mounting-holes-distance 25mm mounting-hole-offset 25mm 9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.41x1.98mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf 62-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, distance of mounting holes - these gaps reduce heat conduction during soldering - ground planes connect to holes - disable for projection From ad96459571a569a983e452184e49702fe8779c4e Mon Sep 17 00:00:00 2001 Images/capsocket.png | Bin 0 -> 136810 bytes Images/captest.png | Bin 0 -> 461484 bytes Panels/title_test_36.stl | Bin 0 -> 74084 bytes Docs/precadsr_layout_front.pdf | Bin 0 -> 10724 bytes 3D Printing/Panels/image.png | Bin 0 -> 9479 bytes main ENV/.gitignore 32 lines usegerberextensions false) (usegerberattributes false) (usegerberadvancedattributes false) (creategerberjobfile false) New KiCad version; non Al panel Gerbers From 5a4e89eea63bf71c8fd68e1168f096dfb3459aa4 Mon Sep 17 00:00:00 2001 Subject: [PATCH 12/13] Update Schematics/schematic_bugs_v1.md Latest commits for file Schematics/SynthMages.pretty/C_Rect_L22.0mm_W6.1mm_P20mm_MKT_BIG_RED_CAP.kicad_mod (grid_origin -1.27 106.172 (grid_origin 121.92 119.38 "Notes": "Layer B.Cu" "Notes": "Layer F.Mask" "Notes": "Layer B.Cu" "Notes": "Layer B.SilkS" ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole Total plated holes Total unplated holes count 16 Not plated through holes are merged with plated holes count 16 Not plated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00 2001 Subject: [PATCH] More traces and vias, and this is good practice, but ho-dang what a mess romps with traces, vias, and net links 06eccf7d9c added the once through idea with commentary by Correcting changed filename in .prl Correcting changed filename in .prl 54f1a61ba5 gets jiggy with PCB locator, 8 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator Samtec HLE.